1. Field of the Invention
The present invention relates in general to a power line noise prevention circuit for a semiconductor memory device, and more particularly to a power line noise prevention circuit which is capable of suppressing noises on supply and ground voltage lines when internal circuits consuming a large current amount are sequentially operated. The present invention is applicable to a data output buffer of a multi-bit dynamic random access memory for suppressing a data output noise, and other devices composed of semiconductor chips.
2. Description of the Prior Art
In constructing a data output buffer in a semiconductor memory device, a conventional problem is a self-noise which is generated when the data output buffer is operated under the condition that it has a high drive power. Such a noise is prominent in multi-bit memories. For example, wide-bit memories such as X8, X16 and X32 are exposed to the output noise problem.
The external environment of a memory chip may be a module in which several chips are arranged. In this case, the memory chip is connected to a system data bus via a data bus of the module. The data output buffer must have a high drive power to sufficiently drive the external data bus. When the data output buffer is operated, a chip internal drive voltage and a ground voltage may be varied in level due to a severe noise. In the case where many drivers with high drive capability are operated simultaneously and, furthermore, in the case where all of them drive high or low states, the result becomes severer. In other words, the chip internal drive voltage is instantaneously lowered when all of the data output buffers output high values at the same time, and the ground voltage is instantaneously raised when all of the data output buffers output low values simultaneously.
In the semiconductor chip, generally, a large electrostatic capacity is present between the chip internal drive voltage and the ground voltage to protect them from noises. Such an electrostatic capacity is formed using an artificial space in the chip, and called a decoupling capacitor. Particularly in a dynamic random access memory (referred to hereinafter as DRAM), the decoupling capacitor is used to offset a bit line sense amplification noise. However, when the data output buffer is operated, the complementary decoupling effect cannot be obtained because the consumed current flows out of the chip in the case of high data and into the chip in the case of low data. To the contrary, the decoupling capacitor between the chip internal drive voltage and the ground voltage induces a mutual noise due to coupling between an chip external supply voltage and the ground voltage. Further, an inductance component is present on a path between the chip external supply voltage and the ground voltage. Such an inductance component induces a ringing phenomenon, thereby causing the supply and ground voltage levels to represent a sinusoidal wave. In other words, in the case of outputting high data, the supply voltage is lowered and then coupled to the ground voltage, resulting in a reduction in the ground voltage level. Also, in the case of outputting low data, the ground voltage is raised and then coupled to the supply voltage, resulting in an increase in the supply voltage level. Because such an operation is instantaneously performed, it is directly connected to the ringing phenomenon, which will be an obstacle to a data read operation. The ringing phenomenon is unavoidable unless ideal infinite power is supplied into the chip. Also, the ringing phenomenon becomes severer as an inductance on a power supply pin becomes higher.
Particularly in the DRAM, a VOL value often becomes an issue because it is relatively lower than a VOH value. For example, in the case where only one of all outputs of a multi-bit memory device has a low value, the supply voltage in the chip is instantaneously lowered and then coupled to the ground voltage, resulting in an instantaneous reduction in the ground voltage level. The resultant ringing phenomenon increases the ground voltage level to the VOL value or more, thereby causing the system bus to misrecognize the data output value as high. As a result, the device does not satisfy a given access time or it suffers a loss for a certain time period.
A conventional method for solving the above obstacle is to decrease the drive speed to reduce the noise. The decreased drive speed is obtained by reducing a size of the driver, making a fan-out small at a stage just before the driver, or attaching a resistance component to a ground voltage source of the driver for the prevention of ground bounce. However, the above-mentioned conventional method is not the fundamental countermeasure in that it degrades an access speed having a direct connection with the memory performance.